1. Field of the Invention
The present invention is related to a power semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device which includes an insulating gate bipolar transistor and a free wheel diode and a method of manufacturing the same.
2. Description of the Related Art
FIG. 33 is a circuitry diagram of an inverter which uses an insulating gate bipolar transistor (hereinafter referred to as an “IGBT”) and a free wheel diode (hereinafter referred to simply as a “diode”). An inverter which is a converter to convert from DC to AC and vice versa is formed by an IGBT, which is a switching element, and a diode. Four or six IGBT/diode elements are used as one set (six elements in FIG. 33) for control of a motor.
A DC terminal of the inverter shown in FIG. 33 is connected with a DC power source, and switching of the IGBTs converts a DC voltage into an AC voltage which is then fed to a motor which is a load. In this inverter, the diodes are connected in a reverse parallel arrangement with the IGBTs so that the diodes and the IGBTs are respectively paired.
FIG. 34 is a cross sectional view of a semiconductor device generally denoted at 1000 in which an IGBT and a diode are incorporated within one element, which is a structure containing the IGBTs and the diodes (JP, 2005-57235, A).
The semiconductor device 1000 includes an N− substrate 1. On the N− substrate 1, a P base layer 2 is selectively formed through an N layer 4. Emitter regions 3 containing a high concentration of n-type impurities are selectively formed on the P base layer 2.
There are grooves 7 which extend from the emitter regions 3 to the N− substrate 1. Gate insulation films 8 are formed on the inner walls of the grooves 7, and gate electrodes 9 of poly-silicon are disposed further inside. The P base layer 2 located between the emitter regions 3 and the N layer 4 serves as a channel region.
Inter-layer insulation films 10 are disposed on the emitter regions 3. An emitter electrode 11 is formed so that it contacts parts of the emitter regions 3 and the P base layer 2.
The back surface of the N− substrate 1 seats an N+ cathode layer 5 and a P+ collector layer 6, and a collector electrode 13 is formed on the back surfaces of the N+ cathode layer 5 and the P+ collector layer 6.
An operation of the IGBT 1000 is basically the same as that of an ordinary IGBT. There is however the N layer 4 disposed, and therefore, while the IGBT is ON, the N layer 4 serves as a barrier against holes implanted from the P+ collector layer 6, which makes it difficult for the holes to move to the P base layer 2. This accumulates carriers near the N layer 4 and lowers the ON-voltage of the IGBT 1000. When the IGBT is OFF, the N layer 4 gets depleted at a collector voltage and the influence of the N layer 4 disappears.
There nevertheless is a problem with the semiconductor device 1000 that since the semiconductor device 1000 internally includes the diodes, VF (forward-direction breakdown voltage) of the diodes increases when the gates of the IGBTs turn on.
There is another problem that when helium ions (lifetime killer) are implanted into the N layer 4 in an attempt to shorten the lifetime of carriers inside the N layer 4 and reduce a recovery current (denoted at Irr in FIG. 35), a VF increase at the diodes caused by turning on of the gates of the IGBTs becomes greater than a VF increase as it is in the OFF-state.